中国信息产业网 - 一种基于FPGA的时钟数据恢复电路的设计实现 关键词： 时钟数据恢复；过采样；输入延时单元；现场可编程逻辑阵列 [gap=784]Keywords: clock data recovery; over-sample; IDELAY; FPGA
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时钟数据恢复电路(Clock Data Recovery,CDR)是实现高速串行传输技术的关键模块。它从串行数据中恢复出时钟信号,并通过数据恢复技术消除数据在传输过程...
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clock and data recovery 时钟数据恢复 ; 时钟与数据恢复 ; 资料与时脉恢复器
dual-loop clock and data recovery 双环时钟数据恢复
Clock and Data Recovery Circuit 时脉与资料回复电路
clock and data recovery cdr 时钟和数据恢复
parallel clock and data recovery 并行时钟数据恢复
Clock and Data Recovery Circuits 时钟与数据恢复电路
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
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